[1825 days] Verification Techniques for System-Level Design

[1825 days] Verification Techniques for System-Level Design

0 đánh giá

CHI TIẾT SẢN PHẨM

Mã sản phẩm:

9780123706164

Tồn kho:

Còn hàng

Danh mục

Mua eTextbooks trực tuyến

Nhà xuất bản:

Elsevier S & T

Trạng thái:

Có hàng

Loại bìa:

Page Fidelity

Ngôn ngữ:

English

Tác giả:

Fujita, Masahiro; Ghosh, Indradeep; Prasad, Mukul

Special Price 2,463,000 VNĐ

Còn 100,000,000,000,000,000 VNĐ nữa bạn sẽ được miễn phí giao hàngTìm hiểu thêm

Mua hàng số lượng lớn

Thời gian giao hàng Xem thêm

Chính sách đổi trả Xem thêm

Số lượng

Mô tả
Đánh giá (0)

This book will explain how to verify SoC (Systems on Chip) logic designs using “formal and “semiformal verification techniques. The critical issue to be addressed is whether the functionality of the design is the one that the designers intended. Simulation has been used for checking the correctness of SoC designs (as in “functional verification), but many subtle design errors cannot be caught by simulation. Recently, formal verification, giving mathematical proof of the correctness of designs, has been gaining popularity.

For higher design productivity, it is essential to debug designs as early as possible, which this book facilitates. This book covers all aspects of high-level formal and semiformal verification techniques for system level designs.

• First book that covers all aspects of formal and semiformal, high-level (higher than RTL) design verification targeting SoC designs.
• Formal verification of high-level designs (RTL or higher).
• Verification techniques are discussed with associated system-level design methodology.

[1825 days] Verification Techniques for System-Level Design

Sản phẩm liên quan

Trang chủ

Tài khoản

Giỏ hàng

Thanh toán